Technology
Hardware-grade performance.
We build every layer of our stack in-house, from FPGA bitstreams and kernel modules to strategy engines and risk systems. Vendor lock-in is an unacceptable latency tax.
FPGA Infrastructure
Critical path logic — order encoding, packet parsing, CRC validation, quote generation, and hardware kill-switch enforcement — lives on Xilinx Alveo and custom PCIe FPGA cards. Offloading these functions from the host CPU eliminates OS scheduling jitter and reduces wire-to-decision latency to under 200 nanoseconds.
FPGA bitstreams are developed using a combination of vendor HLS toolchains and handwritten RTL (VHDL / SystemVerilog). Our engineers maintain a hardware simulation suite that runs alongside CI/CD to catch regressions in timing closure before synthesis.
Co-location & Network Topology
Servers are co-located in carrier-neutral data centres adjacent to the matching engines of the exchanges we trade. Physical cross-connects and direct market access (DMA) feeds replace public internet paths. We use PTP-synchronised hardware clocks (sub-100 ns accuracy) for timestamping order events, enabling latency attribution down to the nanosecond boundary.
Network topology is continuously monitored by our infrastructure team. Route changes are caught within seconds via active probing; failover occurs automatically without strategy interruption.
C++ / Rust Engineering Stack
The order management system, risk engine, and market-data handler are written in C++20 with careful attention to allocation patterns, cache locality, and branch-predictor behaviour. Hot paths are profiled with perf and Intel VTune; any regression above 50 ns triggers a mandatory review.
Infrastructure components — configuration management, monitoring agents, and deployment tooling — are written in Rust, favouring its ownership model for correctness guarantees in systems that must not panic. We are migrating portions of the strategy runtime to Rust incrementally, where the safety guarantees provide operational value without latency cost.
Zero-downtime deployment.
Production strategy changes are deployed via a blue-green promotion pipeline. Each build must pass deterministic latency benchmarks, risk-limit regression tests, and a strategy-level back-test before promotion. Canary traffic allows live A/B comparison before full switchover.
Full-stack telemetry.
Every order event, market-data update, and risk-limit evaluation is timestamped at nanosecond resolution and written to a columnar time-series store. Post-trade analysis compares expected vs realised latency distributions for each session.